It is well known that multiplying a vector by a matrix (vector matrix multiplication) can be performed using three-terminal memory cells, which may be floating gate cells or other cells with suitable properties, to represent the values stored in the matrix. Electric charge is pulsed individually into such three-terminal memory cells, which may be arranged in geometrical correspondence to the matrix elements, to set an “effective channel resistance” of each cell that represents the corresponding matrix value.
The effective resistance may be considered to be, more strictly speaking, the amount of current allowed to flow in the three-terminal memory cell from source to drain for a particular gate voltage. Changing the amount of charge in the three-terminal memory cell changes the threshold voltage for allowing current flow between the source drain; hence for a given gate voltage, the amount of current that will flow from source to drain is altered when the amount of charge is altered. In some current-voltage regimes, this relationship can be approximated in terms of a resistance, hence the term “effective resistance” is adopted here.
When charge is pulsed into a three-terminal memory cell, the memory cell undergoes some physical change. For example, charge may be trapped in the device, ions may move in the device, or atoms within the device may become rearranged. For convenience herein, this will be referred to as the physical state of the device. The cells employed may be known suitable types such as silicon-oxide-nitride-oxide-silicon (SONOS), floating polygate transistors, EEPROM, NAND flash bit cells, NOR flash bit cells, or the like. Although not required, such elements will often have a floating-gate metal oxide semiconductor (MOS) transistor. When MOS transistors are employed in the cells, the transistors may be arranged to have a floating gate that is electrically isolated from ground, thus allowing it to store and retain charge. As will be readily recognized, the amount of charge depends on the voltage level and duration of the pulses used to program the cell.
The channel current between the source and drain of each cell for a given read-operation gate voltage is determined by the physical state of the device, i.e., it is a function thereof. For floating gate transistors, the physical state is determined by how much charge is floating in its gate. Therefore, each cell may be individually programmed by supplying voltage pulses to it until the stored charge, and the resulting current, corresponds to the value the cell is supposed to represent.
Other three-terminal devices, such as ferroelectric FETs, that also use a stored state to modify the channel conductance may also be used. Similarly, three-terminal programmable resistors may also be used. Changing the channel current by changing the physical state is equivalent to changing the effective channel resistance. For convenience herein, generally all types of such three-terminal devices that are suitable to be employed for such vector matrix multiplication will be referred to as three-terminal memory cells. Also for convenience herein, it should be understood that for devices that are not floating gate cells, adding charge or removing charge should be defined as changing the physical state by supplying charge to the gate or removing charge from the gate.
Each element of a vector that is to be multiplied by the matrix is represented by a voltage that is applied to the source terminals of all of the cells along a corresponding row of the matrix. The resulting currents from the drains are integrated along the columns so as to produce a summed current. The current may be applied to an analog-to-digital converter (ADC) to produce a digital representation of the value represented by the total of each column current.